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MatX

Category: AI Chips / Semiconductors

Specialized AI chips purpose-built for Large Language Models (LLMs), delivering 10x computing power for training and inference workloads compared to traditional GPUs. MatX was founded in 2022. The company is led by Reiner Pope. Based in Mountain View, United States. Team size: 100. Total funding raised: $620.0M. Latest round: Series B. Key investors include ["Jane Street","Situational Awareness LP","Spark Capital"].

Founded
2022
Headquarters
Mountain View, United States
Team size
100
Total funding
$620.0M

Value proposition

Delivers higher throughput than any announced product while matching best-in-class latencies by combining SRAM-first architecture for low latency with HBM for long-context support, enabling >2000 output tokens/second for large models.

Products and solutions

["MatX One chip - flagship AI accelerator","SRAM-optimized weight storage system","HBM-based long-context KV storage","Advanced scale-up interconnect technology","Custom numerics optimization for transformers"]

Unique value

Only chip designed from ground-up specifically for LLM workloads, combining SRAM-first design for low-latency inference (enabling >2000 output tokens/second) with HBM for long-context support. Achieves highest FLOPS/mm² and most scale-up interconnect of any product, with streamlined architecture eliminating unnecessary GPU components.

Target customer

Frontier AI labs, large enterprises deploying LLMs, cloud service providers, and organizations running AI workloads with 7B+ parameter models (ideally 20B+ parameters)

Industries served

["Artificial Intelligence / Machine Learning","Semiconductors","High-Performance Computing","Cloud Infrastructure","Data Centers","Enterprise AI Applications"]

Technology advantage

Founded by Google TPU architects (Reiner Pope - world's fastest LLM inference software creator, and Mike Gunter - 11-chip designer) to create chips 10x better than Nvidia GPUs for LLM training and inference. Proprietary approach uses weights in SRAM for low latency while storing key-values in HBM for long context, supporting large transformer models with thousands of simultaneous users. Platform-agnostic design allows broader market access than cloud-locked solutions.

How they differentiate

LLM-specialized chips with SRAM-first architecture for low latency (>2000 output tokens/second) combined with HBM for long-context support, designed by former Google TPU architects to deliver 10x better performance than GPUs for large model training and inference

Main competitors

["Nvidia","Etched","AMD"]

Key partnerships

["Spark Capital (Series A lead investor)","Jane Street (Series B lead investor)","Situational Awareness LP (Series B co-lead)","Nat Friedman and Daniel Gross fund (early investor)","Marvell Technology (strategic investor)","Strategic manufacturing and supply chain partnerships (details undisclosed)","Multiple undisclosed frontier AI lab partnerships for chip testing"]

Notable customers

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Major milestones

["Founded by Google TPU architects Reiner Pope and Mike Gunter in November 2022","Raised $25M Seed round led by Nat Friedman and Daniel Gross (March 2024)","Secured ~$80M Series A led by Spark Capital at $300M+ valuation (November 2024)","Raised $500M+ Series B led by Jane Street and Situational Awareness LP (February 2026)","Proved out all technical bets and secured necessary partnerships for chip development","One of the largest early-stage semiconductor funding rounds on record"]

Growth metrics

Grown to 100 employees; completed technical validation across ML numerics, chip design, and system architecture

Market positioning

Early-stage challenger to Nvidia's AI chip dominance, targeting frontier AI labs and enterprises running 7B+ parameter models

Geographic focus

United States (Mountain View, CA) with global market reach

Patents and IP

CEO Reiner Pope holds 11 patents in ML and chip design from his Google tenure; specific MatX patents not publicly disclosed

About Reiner Pope

Former Google Senior Staff Software Engineer and Efficiency Lead for Google PaLM. Designed and implemented the world's fastest LLM inference software. Architect and Compiler Lead for Google's ML chips, helped conceive Google's TPU v5e. Over 10 years experience in high-performance software and hardware across the stack from ML chips to distributed system infrastructure to LLMs. Holds 11 patents. Google Scholar citations: 11,513.

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