Tattvam AI
Category: AI Infrastructure
AI-powered semiconductor chip design automation platform that builds reasoning models to understand circuit structures from first principles and automate the RTL-to-GDSII physical design process, reducing development cycles from years to weeks. Tattvam AI was founded in 2025. The company is led by Bragadeesh Suresh Babu. Based in London, United Kingdom. Team size: 2-5. Total funding raised: $1.7M. Latest round: Pre-Seed round ($1.7M, Feb 2026). Key investors include ["Seedcamp (lead investor)","EWOR","Entropy Industrial Ventures","Concept Ventures","Stan Boland (semiconductor angel investor, former CEO of Icera and Element 14)"].
- Founded
- 2025
- Headquarters
- London, United Kingdom
- Team size
- 2-5
- Total funding
- $1.7M
Value proposition
Dramatically compresses chip development timelines from 2-3 years to weeks by building an AI reasoning layer that understands circuits from first principles—constraints, trade-offs, and interdependencies—and autonomously solves complex physical design tasks that currently require months of expert engineering iteration. Makes custom silicon accessible to more companies while reducing development costs by tens of millions of dollars.
Products and solutions
["AI Reasoning Engine for Physical Design (RTL-to-GDSII)","Automated Timing Closure Assistant (initial product focus)","Circuit Structure Analysis & Optimization Platform","First-Principles Reasoning Models for Semiconductor Design"]
Unique value
Pioneering AI systems that reason about circuit structures from first principles rather than pattern matching. Uses mathematical reasoning-inspired AI models to understand constraints, trade-offs, and interdependencies in chip design. Employs synthetic datasets inspired by ARC-AGI benchmarks and mathematical theorems to train domain-specific models at low cost. Focus on local AI systems that ensure data confidentiality while providing human-engineer-level insights in hours instead of months.
Target customer
Fabless semiconductor companies, chip design service providers (ASIC design firms), hyperscalers building custom silicon (Google, Microsoft, Meta), automotive chip developers, and companies requiring specialized AI/ML hardware accelerators
Industries served
["Semiconductor & Chip Design","AI/ML Hardware Acceleration","Custom Silicon Development","Electronic Design Automation (EDA)","Deep Tech Infrastructure","Automotive Semiconductors","Data Center & Cloud Computing Hardware"]
Technology advantage
First-mover in building specialized reasoning models for physical design automation (RTL-to-GDSII), targeting the most labor-intensive bottleneck in chip development. Complements rather than competes with existing EDA tools from Synopsys/Cadence by adding an intelligence layer on top. Addresses critical industry constraint: the small pool of experienced semiconductor engineers and 2-3 year design cycles. Their approach can handle the iterative loops in timing closure, clock tree synthesis, and placement/routing that currently take months. Backed by semiconductor veterans who understand the market need. Plans to expand from initial wedge (timing closure) to full physical design automation.
How they differentiate
First-mover in building specialized reasoning models for physical design automation (RTL-to-GDSII) that understand circuits from first principles—constraints, trade-offs, and interdependencies—rather than pattern matching. Uses mathematical reasoning-inspired AI with synthetic datasets (ARC-AGI benchmarks) and focuses on local AI systems ensuring data confidentiality. Complements existing EDA tools from Synopsys/Cadence by adding an intelligence layer on top, rather than replacing them. Initial entry wedge targeting timing closure challenges before expanding to full physical design automation.
Main competitors
["ChipAgents (Alpha Design AI)","Synopsys","Cadence Design Systems"]
Key partnerships
["Exploratory discussions with semiconductor foundries","Initial conversations with EDA vendors for workflow integration","Engagement with chip design service companies (target customers include Alchip Technologies, Aion Technology, Ensilica)","Collaborations with leading chip design teams globally (in development)"]
Notable customers
[]
Major milestones
["Company founded in 2025 by Bragadeesh Suresh Babu and Lannan Jiang in London","Successfully exited stealth mode in February 2026 with $1.7M pre-seed funding","Attracted investment from semiconductor veterans including Stan Boland (former CEO of Icera acquired by NVIDIA, and Element 14 acquired by Broadcom)","Recognized as part of emerging Indian-origin semiconductor startup ecosystem with strategic focus on India's semiconductor opportunity"]
Growth metrics
Just emerged from stealth mode in February 2026 with $1.7M pre-seed funding; currently 2-5 team members with plans to expand to 5 people soon; first product launch planned in coming months; holding exploratory discussions with semiconductor foundries, EDA vendors, and chip design firms globally
Market positioning
Early-stage deeptech startup positioning as an 'intelligence layer' for semiconductor chip design, specifically targeting the labor-intensive physical design stage. Complements rather than competes with established EDA tools. Targets the critical bottleneck in chip development where 2-3 year cycles can be compressed to weeks. Currently pre-revenue with first product launch planned in coming months.
Geographic focus
Headquartered in London, United Kingdom with strong strategic focus on India's semiconductor ecosystem (founder is IIT Madras alumnus). Engaging with global semiconductor design teams across Europe, India, and North America.
Patents and IP
No registered patents publicly disclosed as of February 2026 (company just emerged from stealth)
About Bragadeesh Suresh Babu
IIT Madras alumnus with strong mathematics background from competitive olympiads. Early engineer at UK-based brain-monitoring startup CoMind (which raised $100 million) and one of the earliest engineers at UK-based chip startup Fractile, where he built AI inference chips targeting state-of-the-art large language models. Turned down an offer to join Google's TPU team to found Tattvam AI in 2025.
Official website: https://www.tattvamlabs.ai/