d-Matrix to integrate Raptor inference chips with Nvidia NVLink Fusion for 2027 servers
The AMW Read
Concrete NVLink Fusion/MGX cohabitation and 2027 timeline meaningfully update the known Nvidia–d-Matrix chip partnership; silicon architecture is the headline, with segment-level impact on inference infra.
d-Matrix to integrate Raptor inference chips with Nvidia NVLink Fusion for 2027 servers
d-Matrix will connect its next-generation Raptor inference accelerators to Nvidia’s data-center stack through NVLink Fusion, placing the chips inside Nvidia MGX rack architectures rather than standing up a separate fabric. Compatible systems are expected in 2027, while d-Matrix aims to finish Raptor’s design phase in 2026. The U.S., Microsoft-backed startup—described in the report as valued at about $2 billion—is targeting inference workloads such as chatbots, programming assistants, and voice agents as models shift from training into continuous production use. The announcement extends July’s Nvidia–d-Matrix collaboration by naming the interconnect path and a concrete rack timeline.
The strategic signal is cohabitation, not displacement. Specialized inference silicon that rides Nvidia’s interconnect, networking, cooling, and supply chain can compete on cost and latency for serving while leaving the dominant “AI factory” footprint intact. That matters as capital and operator attention move toward daily inference: challenger accelerators win adoption only if they plug into the racks operators already buy. Per the AI Market Watch index, d-Matrix has raised $450M in total funding (coverage across ~5,000 indexed companies), capital now tied to a clearer path into Nvidia-shaped deployments if the 2027 systems ship.
For builders and investors, diligence shifts from raw ASIC-versus-GPU claims to whether operators will mix Raptor into MGX fleets under NVLink Fusion—and whether that mix softens Nvidia’s rack-level control or further entrenches it as the default integration layer through 2027.
