SUNMMIO completes Pre-A2 and Series A rounds to advance 3D-stacked inference chips
The AMW Read
The financing advances an inference-chip entrant with a specific stacked-memory architecture, but undisclosed round sizes and absent production benchmarks limit the demonstrated impact to its sub-segment.
SUNMMIO completes Pre-A2 and Series A rounds to advance 3D-stacked inference chips
Beijing-based SUNMMIO has completed Pre-A2 and Series A financing led by Beijing state-backed investment platforms, including Yizhuang State Investment. The inference-chip developer has raised nearly RMB 2 billion in total over the past year; the report does not disclose the amounts of the latest rounds separately. It plans to expand its R&D team, advance its technology and accelerate mass production of its proprietary 3D TokenPU processors. Its first-generation A4E chip completed tape-out in June.
The technical focus is memory movement in large-model inference. SUNMMIO's design stacks eight memory wafers above a logic wafer and claims memory bandwidth of 16 terabytes per second, targeting data-transfer bottlenecks that constrain inference performance. This places the company in the AI infrastructure market's competition over accelerator architecture: its proposed advantage centers on how memory feeds computation. The stated bandwidth is a design claim, however, and the report supplies no workload benchmarks or production results demonstrating how it translates into useful inference throughput.
For builders and investors, the concrete question is whether SUNMMIO can turn its tape-out milestone and funding into production hardware with measurable workload benefits. Tape-out marks progress toward that objective, but does not establish manufacturing readiness or customer economics. Evaluation should therefore distinguish the nearly RMB 2 billion raised across a year from the undisclosed latest-round proceeds, and assess the bandwidth claim alongside demonstrated inference performance and evidence of mass-production execution.
