Positron AI closes $875M Series C at $5B to tape out LPDDR5X inference ASIC Asimov
The AMW Read
$875M at $5B updates the AI-infra player map with a mega capital signal behind a commodity-memory inference ASIC thesis, a structural silicon bet before Asimov silicon exists.
Positron AI closes $875M Series C at $5B to tape out LPDDR5X inference ASIC Asimov
Reno-based Positron AI closed an $875 million Series C at a $5 billion post-money valuation—about five times the $1 billion-plus mark after its $230 million Series B in February 2026. Proceeds fund tapeout of Asimov, a custom inference ASIC on TSMC N3P aimed for late 2026, with production slated for the second half of 2027. Unlike Nvidia GPUs that rely on scarce High Bandwidth Memory and CoWoS packaging, Asimov uses commodity LPDDR5X on an organic substrate. The raise landed two days after Qualcomm and Amazon disclosed a multi-generational LPDDR inference partnership of up to $60 billion in purchases, an independent vote for the same memory thesis.
The market timing is structural: Gartner reported in August 2026 that global AI inference spend ($23.3 billion) overtook training ($19 billion) for the first time, while AI-optimized infrastructure grew 96% year over year to $42.3 billion. HBM supply is the bottleneck—demand rising ~60% annually, with limited CoWoS capacity—and Positron investor Forest Baskett of NEA cited reports that Nvidia’s Rubin Ultra cut planned HBM4E from a terabyte to about 192GB for lack of supply. Positron’s claim is that inference decode is memory-bound and sequential, so GPU deployments often use under 30% of peak bandwidth while its memory-first design targets over 90% utilization, making effective bandwidth competitive even when peak specs are not. Those utilization figures and Asimov performance targets remain company-stated and unverified; third parties have flagged that Atlas comparisons need independent checks, and Asimov has not taped out.
For builders and investors, the near-term signal is capital and supply-chain, not proven silicon: a $5B valuation now prices the LPDDR-for-decode wager before production silicon arrives in 2027. Watch whether independent measurements close the gap The Register highlighted—Asimov’s ~2.76 TB/s realizable bandwidth design target versus Rubin’s ~22 TB/s peak HBM—and whether commodity-memory ASICs can win allocation where HBM and CoWoS remain constrained.
