Rapidus Corporation
Category: AI Chips / Semiconductors
Japanese government-backed semiconductor startup developing and manufacturing 2nm-generation logic semiconductors for AI, high-performance computing, and data center applications. Rapidus Corporation was founded in 2022. The company is led by Dr. Atsuyoshi Koike. Based in Chiyoda, Tokyo, Japan. Total funding raised: $2.7B. Latest round: Venture Round. Key investors include Government of Japan (IPA/METI), Canon Inc., Fujitsu, NTT, SoftBank, Sony Group, Toyota Motor Corporation, Denso, NEC, Kioxia, MUFG Bank, Development Bank of Japan.
- Founded
- 2022
- Headquarters
- Chiyoda, Tokyo, Japan
- Total funding
- $2.7B
Value proposition
Japan's only advanced-node (sub-3nm) logic foundry, offering 2nm GAA technology with competitive wafer pricing (~$20,000/wafer), government-backed stability, and the world's shortest time-to-market through AI-agentic design tools and close collaboration with ecosystem partners
Products and solutions
2nm GAA (Gate-All-Around) logic semiconductors, 2HP process (237 MTr/mm² transistor density), AI-Agentic Design Solution (Raads) integrated with Cadence InnoStack, 3D packaging technology, chiplet design and manufacturing, IIM-1 fab in Chitose, Hokkaido (25,000 wafers/month capacity)
Unique value
Japan's national champion for advanced semiconductor manufacturing — the only foundry outside Taiwan and Korea capable of 2nm GAA production, backed by $16B+ in government subsidies and 32 major Japanese corporations
Target customer
AI chip designers, HPC/data center operators, edge computing companies, robotics firms, and global semiconductor customers needing advanced 2nm foundry services
Industries served
AI/ML accelerators, High-Performance Computing, Data Centers, Edge Computing, Robotics, Telecommunications (5G/6G), Automotive
Technology advantage
2nm GAA (Gate-All-Around) nanosheet FET technology licensed from IBM; 237 MTr/mm² transistor density; ASML EUV lithography tools; AI-agentic EDA design flow (Raads + Cadence InnoStack); chiplet and 3D packaging capabilities; Japan-U.S. government collaboration framework
How they differentiate
National government backing (METI/IPA) providing long-term capital stability; aggressive 2nm wafer pricing (~$20K vs TSMC's higher rates); AI-agentic design solution (Raads) with Cadence for 2X faster design turnaround; IBM GAA technology licensing; IMEC research collaboration; single-wafer-processing innovation focus
Main competitors
TSMC (Taiwan), Samsung Foundry (South Korea), Intel Foundry Services (USA)
Key partnerships
IBM (2nm GAA technology development), IMEC (research collaboration, Core Partner Program), Cadence (AI-Agentic Design Solution Raads), Tenstorrent (AI edge IP partnership), ASML (EUV lithography tools), Canon, Fujitsu, NTT, SoftBank, Sony Group, Toyota
Notable customers
Tenstorrent (AI chip design), 60+ companies reportedly interested in 2nm chips for AI, robotics, and edge computing (as of Feb 2026), in talks with Apple and Google for mass production (per Nikkei, April 2025)
Major milestones
Founded August 2022 with 8 major Japanese corporate backers, Dec 2022: IBM partnership for 2nm GAA technology, Feb 2023: Selected Chitose, Hokkaido for IIM-1 fab, Apr 2023: Joined IMEC Core Partner Program, Aug 2025: Produced 2nm GAA test chip using ASML EUV tools, Nov 2025: Selected by METI as operator for national semiconductor production, Feb 2026: Raised ¥267.6B ($1.7B) from government and 32 private companies, Jun 2026: Additional ¥150B ($943M) from IPA, total capital reaches ¥424.95B (~$2.7B), Apr 2026: Japan approved ¥631.5B ($4B) in additional subsidies
Growth metrics
Capital grew from ¥7.3B (Aug 2022) to ¥424.95B (Jun 2026); 1,024 employees (Dec 2025); IIM-1 fab targeting 25,000 wafers/month by 2027; 60+ prospective customers for 2nm chips
Market positioning
Japan's national champion aiming to reclaim advanced semiconductor leadership; positioned as a viable third option alongside TSMC and Samsung for 2nm-class foundry services, with competitive pricing and government-backed stability
Geographic focus
Global (Japan-headquartered, targeting worldwide AI/HPC chip customers, with strong Japan government support and US-Japan collaboration framework)
Patents and IP
2nm GAA nanosheet FET technology (licensed from IBM); AI-Agentic Design Solution (Raads) co-developed with Cadence; chiplet and 3D packaging IP
About Dr. Atsuyoshi Koike
Ex-President of Western Digital Japan (2018-2022); Senior Vice President at SanDisk (2006-2016); President of Trecenti Technologies; Head of Production Technology at Hitachi's Semiconductor Group. B.S. and M.S. in Materials Science and Engineering from Waseda University; Ph.D. in Electronic Engineering from Tohoku University.
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Official website: https://www.rapidus.inc/en/