Skip to main content

XCENA

Category: AI Chips / Semiconductors

South Korean fabless semiconductor startup building CXL-based computational memory chips (MX1) that perform data orchestration and KV cache management directly within memory modules to eliminate AI inference memory bottlenecks. XCENA was founded in 2022. The company is led by Jin Kim (김진영). Based in Pangyo, Seongnam, Gyeonggi-do, South Korea; Sunnyvale, California, USA. Team size: 90+. Total funding raised: $185M. Latest round: Series B. Key investors include Atinum Investment; IMM Investment; Corstone Asia; SBI Investment; Mirae Asset Capital; SV Investment; STIC Ventures; LB Investment; Industrial Bank of Korea; WONIK Investment Partners; TONY Investment.

Founded
2022
Headquarters
Pangyo, Seongnam, Gyeonggi-do, South Korea; Sunnyvale, California, USA
Team size
90+
Total funding
$185M

Value proposition

XCENA's MX1 chip places compute capabilities directly inside memory modules using CXL 3.2, handling KV cache management, preprocessing, and data caching near DRAM — eliminating costly round trips between CPUs, GPUs, and memory during AI inference. The company claims this can reduce server requirements by up to 10x.

Products and solutions

MX1 Computational Memory Chip — CXL 3.2-compliant memory controller combining pooled DDR5 memory with thousands of in-house RISC-V near-data processing cores; handles KV cache management, vector search, data preprocessing, and analytics directly in memory modules. XCENA SDK for software integration.

Unique value

World's first computational memory controller supporting CXL 3.X with thousands of proprietary RISC-V cores integrated directly into the memory hierarchy, enabling near-data processing that offloads memory-intensive AI inference bottlenecks from CPUs and GPUs.

Target customer

Hyperscalers (cloud providers spending tens of billions annually on AI infrastructure), telcos, research institutions, and enterprises with large-scale AI inference workloads.

Industries served

AI/ML infrastructure; Cloud data centers; High-performance computing (HPC); Vector databases; Enterprise AI inference

Technology advantage

CXL 3.2 compliance with PCIe 6.0; thousands of custom RISC-V cores (vs. handful of general-purpose cores in competitors' designs); vertically designed in-house memory hierarchy, interconnect bus, and DRAM controller; Samsung 4nm foundry manufacturing; full-stack SDK for rapid deployment; near-data processing paradigm that dramatically reduces data movement costs.

How they differentiate

XCENA integrates compute directly into memory (near-data processing) via thousands of custom RISC-V cores, not just memory pooling/expansion. Their MX1 chip handles KV cache management and data orchestration tasks within memory modules — the only CXL 3.2 computational memory controller with thousands of cores. Competitors focus on fabric/switching (Panmnesia, UnifabriX) or memory controllers with few general-purpose cores (Astera Labs, Marvell). XCENA also designs its own full memory hierarchy, interconnect bus, and DRAM controller in-house.

Main competitors

Astera Labs (Nasdaq: ALAB); Marvell Technology (Nasdaq: MRVL); Panmnesia; UnifabriX; Fadu

Key partnerships

KISTI (Korea Institute of Science and Technology Information) — MoU for next-gen supercomputing technology development and CXL-based composable memory architecture verification; Samsung Foundry — MX1 chip manufacturing on 4nm process; CXL Consortium member.

Notable customers

Targeting hyperscalers (unnamed); in early-stage conversations with multiple global memory vendors.

Major milestones

Founded as MetisX (Jan 2022); Seed round (early 2022); Series A $44M (May 2024); Won FMS 2024 'Most Innovative Memory Startup' award; Won KAIST 'Innovation Startup Award' (Sep 2024); Rebranded from MetisX to XCENA (Dec 2024); Named among '10 Hottest Semiconductor Startups of 2024' (Jun 2024); Won FMS 2025 Best of Show Award for MX1 computational memory (2025); Showcased MX1 at OCP Global Summit (2025); Partnered with KISTI for supercomputing tech (Nov 2025); Series B $135M at $570M valuation (Apr-May 2026); Mass production of MX1 on Samsung foundry lines scheduled for end of 2026.

Growth metrics

83 employees (Apr 2026); 23 patents; MX1 chip prototype demonstrated; mass production planned H2 2026.

Market positioning

Early-stage challenger in the CXL memory compute space, differentiated from Nasdaq-listed incumbents Astera Labs and Marvell by a vertically integrated design with thousands of proprietary RISC-V cores vs. general-purpose cores, and in-house memory hierarchy/interconnect/DRAM controller. Valued at $570M post-Series B.

Geographic focus

Global (headquarters in South Korea with US office in Sunnyvale, CA; targeting worldwide hyperscaler market)

Patents and IP

23 registered patents in South Korea (as of 2025-07); CTO Dohun Kim holds 40+ US patents in SoC architecture, microprocessor, cache, and memory design.

About Jin Kim (김진영)

Former Corporate VP at SK hynix (one of the youngest executives), lead of Next-Generation Architecture Development Team; experience at Samsung Electronics and SK Telecom; Bachelor's in Computer Science from Seoul National University.

Official website: